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HOBBY FPGA PROJECT · PARTICLE ANIMATION

FPGA Fireworks Simulator

Rockets rise, burst into colorful particles, and fade under gravity. A VHDL particle animation project for the original Zybo and 720p HDMI.

Browser illustration of the particle animation. This is not a board recording or RTL simulation.

A sky generated in hardware

The FPGA Fireworks Simulator targets the original Zybo XC7Z010. Four staggered rockets climb through a dark sky and explode into red, cyan, gold, and magenta sparks. The VHDL design calculates position, velocity, gravity, lifetime, color, and animation timing without a CPU application or software framebuffer.

Particle physics

Four groups contain one rocket and eight sparks each: 36 particle slots in total. Positions use fixed-point arithmetic with four fractional bits. Lookup-table velocities send sparks in eight directions; gravity bends their paths downward, and lifetime controls fading. A deterministic pseudo-random generator varies launch locations.

Architecture

Notebook-style illustration of the block diagram of Zybo video timing, particle state, color pipeline and HDMI output
Fireworks architecture: blanking-time state updates and a seven-stage pixel pipeline. Open the diagram to view it at full size.

The update engine processes one particle per clock, completing all 36 slots during vertical blanking. Particle state stays stable throughout the active image. A balanced, registered color-combining tree aligns RGB and sync through seven pipeline stages.

How particles change each frame

Notebook-style illustration of the flow diagram showing rocket launch, eight-direction explosion, fixed-point gravity, fading and particle expiry
Particle update flow matching the current VHDL design.

Board controls

  • BTN0: reset the animation and video timing.
  • SW2: freeze or resume the particle animation.
  • LED0: video clock locked; LED1: animation heartbeat; LED2: freeze status.

Validation & current status

GHDL simulation and portable synthesis passed. Tests check deterministic launch, explosion position and color, velocity, gravity, fading, freeze behavior, blanking, sync alignment, and reset. Vivado synthesis, placement, routing, and bitstream generation passed. Setup slack is +0.638 ns and hold slack is +0.068 ns. The complete design uses 7,300 LUTs, 3,164 registers, no block RAM, and three DSPs in the reused HDMI encoders. Ten DRC warnings cover DSP input pipelining and the PL-only configuration; there are no DRC errors. Physical board testing is pending.

Scope

This initial version draws 3 × 3 pixel particles on a black background. It targets the original Zybo XC7Z010, using the existing 720p HDMI pipeline. It requires a compatible display. The board constraints are not for the Zybo Z7.