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HOBBY FPGA PROJECT · PROFILING & VERIFICATION

IPScope — Hardware IP Profiling

A standalone FIFO characterization instrument measuring throughput, stalls, occupancy, latency, and data integrity on a 720p HDMI dashboard.

RTL simulation-rendered IPScope dashboard with FIFO measurements and an occupancy bar
Dashboard rendered by the VHDL simulation, supplied in the project documentation. This is not a photograph of a hardware demonstration.

Project demonstration

An automatic browser demonstration of the project concept.

Browser demonstration with synthetic inputs; not a recording of FPGA hardware.

Project overview

IPScope turns the original Zybo Rev B into a standalone instrument for exploring how a synchronous FIFO behaves under different traffic patterns. Traffic generation, sequence checking, measurement, and display run entirely in programmable logic, without Linux, processor software, or an external traffic source.

What is measured?

The device under test is a reusable 256-entry, first-word fall-through FIFO. Each word holds a 32-bit sequence number and a 32-bit insertion timestamp. The timestamp adds instrumentation overhead and measures how long a word remains in the queue.

  • Accepted writes and reads, plus write stalls at full and read stalls at empty.
  • Final and peak occupancy, latency sum and maximum latency in clock cycles.
  • Read sequence mismatches, revealing data corruption or ordering errors.

Each measurement covers 65,536 cycles at 74.21875 MHz. Results are published during video blanking and refreshed once per frame. These are discrete measurement windows, rather than a continuous capture. Dashboard counters are eight-digit hexadecimal; the occupancy bar shows final occupancy.

Traffic modes and controls

  • SW1:0: select balanced traffic, a faster producer, a faster consumer, or deterministic random bursts.
  • SW2: freeze the published dashboard while inspecting results.
  • SW3: invert written sequence data to demonstrate checker failures; switch off to recover on a subsequent clean run.
  • BTN0: reset measurements and video timing; release to restart.

Traffic settings are latched for each run. Allow two frames after a switch change for the new result to appear. LEDs indicate clock lock, published results, freeze, and data errors.

High-level architecture

Traffic generator256-word FIFOSequence checker / latency countersFrame-boundary snapshot720p HDMI dashboard

Notebook architecture

Notebook-style architecture illustration for IPScope
Notebook-style illustration of the documented architecture. Open to view at full size.

Engineering decisions

Measurement and display logic share the pixel clock, avoiding a multi-bit clock-domain crossing for results. External switches and buttons pass through two synchronizer stages. Reset asserts on loss of clock lock and releases through three pixel-clock stages.

The FIFO accepts a simultaneous read and write when full, preserving throughput. At empty, a simultaneous request accepts only the write because there is no empty bypass. Reset clears pointers and occupancy without resetting the memory array. Queued words remaining at the end of a window are reported in final occupancy and discarded before the next run.

Reading the results

For balanced traffic, the documented expected result is 65,536 writes, 65,535 reads, one initial read stall, final and peak occupancy of one, maximum latency of one clock, and zero data errors. Producer-faster traffic fills the FIFO and introduces write stalls; consumer-faster traffic introduces read stalls.

Read throughput equals accepted reads × 74,218,750 / 65,536 words per second. Payload throughput uses four bytes per word, excluding timestamp tags. Average latency is latency sum divided by accepted reads when the read count is nonzero; only words read within the window contribute.

Validation & current status

The repository supplies a simulation-rendered dashboard and verification tests covering FIFO depths 1, 7, and 256, boundary rejection, replacement while full, pointer wraparound, randomized ordering, reset, traffic modes, exact counters and latency, fault injection and recovery, and display alignment. Synthesis and Vivado build scripts are also provided; the build script refuses bitstream generation if setup or hold slack is negative.

No simulation, synthesis, implementation, or physical board test was rerun for this website update. The included preview demonstrates RTL-rendered display output; physical-board measurements and HDMI operation still require validation.

Scope & limitations

This version characterizes one synchronous FIFO on the original Zybo Rev B (XC7Z010-CLG400-1), rather than arbitrary third-party IP or asynchronous FIFOs. Latency is measured in clock cycles, and average occupancy is not measured. Whole-instrument resource reports include video and timestamp overhead, so they do not represent the standalone FIFO’s cost or maximum achievable frequency. The display must accept the fixed 1280 × 720 mode at approximately 59.975 Hz.