Step 1 · Foundations
ZYNQ & HARDWARE/SOFTWARE DESIGN
Zynq PS vs PL: Understanding Hardware/Software Partitioning
A simple guide to choosing what runs in software, what becomes hardware, and how the two work together.
8 min read · Read article →ENGINEERING NOTES
Blog
A step-by-step reading path: start with FPGA foundations, build practical designs, then explore advanced system integration.
Circuit diagrams and board concept illustrations accompany the articles.
Step 2 · Foundations
VHDL DESIGN & VERIFICATION
10 Common RTL Design Mistakes and How to Avoid Them
Practical lessons for FPGA designers, illustrated in VHDL.
10 min read · Read article →Step 3 · Foundations
VHDL & VERIFICATION
Building a Useful VHDL Testbench
Self-checking tests, corner cases, and clear failure messages, explained through a complete counter example.
9 min read · Read article →
Step 4 · Foundations
FPGA DESIGN & TIMING
Understanding Setup and Hold Timing
A practical guide to timing reports, negative slack, pipelining, and choosing the right fix.
7 min read · Read article →
Step 5 · Foundations
FPGA PERFORMANCE & PIPELINING
Throughput vs Latency: A Common FPGA Design Misunderstanding
How a pipeline can take 20 cycles to produce a result while still accepting a new sample every clock.
5 min read · Read article →
Step 6 · Foundations
FPGA ARCHITECTURE & RESET
Why Reset Architecture Matters More Than It Looks
Choosing reset behavior, initialization, and recovery rules for reliable FPGA systems with several clock domains.
5 min read · Read article →
Step 7 · Practical designs
GAME LOGIC & VIDEO
Building a Pong Game in VHDL
How frame-based game updates, debounced controls, and a pixel renderer fit into a small FPGA game.
2 min read
Step 8 · Practical designs
VIDEO & IMAGE PROCESSING
Designing an HDMI Image-Processing Pipeline
A look at streaming filters, matched timing, and memory tradeoffs in a VHDL video pipeline.
2 min read
Step 9 · Practical designs
AUDIO & DIGITAL SIGNAL PROCESSING
Visualizing Audio with a 256-Point FFT
How an audio sample tap, fixed-point FFT, and clock-domain handshakes drive a 32-band HDMI display.
2 min read
Step 10 · Advanced integration
FPGA VERIFICATION & HARDWARE
Simulation Passes—What Comes Next?
What a passing simulation demonstrates, what it leaves open, and how I approach implementation checks and hardware testing.
7 min read · Read article →
Step 11 · Advanced integration
FPGA VERIFICATION & VALIDATION
Why Passing Simulation Is Only the Beginning of FPGA Verification
A practical verification roadmap from checked RTL behavior to timing, board debug, and system-level evidence.
5 min read · Read article →
Step 12 · Advanced integration
FPGA DESIGN & RESET
Reset Design Across Clock Domains
Asynchronous assertion, synchronous release, and a practical VHDL example showing why each clock domain needs its own reset handling.
8 min read · Read article →
Step 13 · Advanced integration
FPGA DESIGN & VERIFICATION
Clock Domain Crossing: Why Two Synchronizers May Not Be Enough
Understanding independent signal arrival, reconvergence, and coherent transfers with handshakes, valid protocols, and asynchronous FIFOs.
8 min read
Step 14 · Advanced integration
FPGA ARCHITECTURE & TIMING
Timing Closure Is an Architecture Problem, Not Just a Tool Problem
How critical paths, pipeline boundaries, FPGA resources, and physical connections shape timing from the start.
5 min read · Read article →Step 15 · Advanced integration
IMAGE PROCESSING · VHDL & HLS
VHDL or HLS: Case Study
What my Sobel filter reveals about streaming image processing, explicit RTL control, and where HLS can make algorithm development easier.
8 min read · Read article →
Step 16 · Advanced integration
FPGA ARCHITECTURE & DESIGN
FPGA Architecture: The Decisions Before the RTL
Pipeline boundaries, shared hardware, clock crossings, and the interface decisions that shape an FPGA design before coding starts.
7 min read · Read article →
Step 17 · Reflection
PERSONAL PROJECTS & ENGINEERING LESSONS
What I Learned Building My FPGA Hobby Projects
How my personal projects reflect the way I approach design, testing, problem-solving, and teamwork.
5 min read · Read article →