PROJECT PORTFOLIO

My FPGA Hobby Projects

Video pipelines, audio processing, games, and debugging tools built while exploring FPGA and embedded design.

PROFESSIONAL PROJECT EXPERIENCE

Experience across industry applications.

Throughout my career at IHSE, 360T / Deutsche Börse Group, Hyundai Mobis, and Inno-Spec, I have worked extensively on FPGA and embedded systems spanning video and image processing, low-latency trading, cybersecurity, audio interfaces, automotive vision, and hyperspectral imaging.

The hobby projects presented here complement my professional experience. I welcome interviews, technical discussions, and opportunities for cooperation where I can share my expertise and discuss my contributions to professional projects at a non-confidential level, consistent with my contractual obligations.

Explore my professional experience →

Personal FPGA projects, documented from the repository. Each case study distinguishes implemented features, recorded validation, and work still in progress. Board images are concept illustrations.

Concept illustration of HDMI video and image processing

HOBBY PROJECT

VIDEO & IMAGE PROCESSING

HDMI Video Interface and Image Processing

An HDMI video pipeline with selectable edge detection, motion detection, cartoon styling, and color corrections.

Automatic demo available

Implemented · hardware validation not documented

VHDLTMDSImage Processing

Concept illustration of FPGA audio spectrum visualization

HOBBY PROJECT

AUDIO & DIGITAL SIGNAL PROCESSING

Audio Spectrum Visualizer

Stereo audio loopback with a 256-point FFT and a 32-band spectrum display over HDMI.

Automatic demo available

Simulation & build passed · hardware testing pending

VHDL256-point FFTHDMI

Concept illustration of an FPGA Pong game

HOBBY PROJECT

GAME LOGIC & VIDEO

Pong Game

Two-player Pong in programmable logic, with onboard button controls, collision detection, and a 720p renderer.

Automatic demo available

Simulation & build passed · hardware testing pending

VHDLGame Logic720p HDMI

Concept illustration of the intended USB webcam-to-HDMI system

IN DEVELOPMENT

EMBEDDED VIDEO · WORK IN PROGRESS

USB Webcam to HDMI

A development project exploring USB webcam capture, frame processing, and HDMI output on PYNQ-Z2.

Automatic demo available

In development

ZynqUSB / UVCHDMI

Simulation-generated logic analyzer display showing UART waveforms and decoded bytes

HOBBY PROJECT

FPGA DEBUGGING & UART

FPGA Logic Analyzer

A self-contained four-channel analyzer with internal UART capture, byte decoding, timing cursors, and a 720p HDMI display.

Automatic demo available

Simulation & implementation passed · hardware testing pending

VHDLUARTBlock RAM

RTL simulation-rendered IPScope dashboard showing FIFO transfer, latency, occupancy, and error counters

HOBBY PROJECT

HARDWARE IP PROFILING & VERIFICATION

IPScope — Hardware IP Profiling

A standalone FIFO characterization instrument measuring throughput, stalls, occupancy, latency, and data integrity on a 720p HDMI dashboard.

Automatic demo available

Simulation preview available · hardware validation pending

VHDLFIFO Profiling720p HDMI

Simulation-rendered Ethernet packet processing dashboard

HOBBY PROJECT

ETHERNET & STREAM PROCESSING

High-Speed Ethernet Packet Processing Engine

A reusable VHDL packet engine with IPv4/IPv6 parsing, UDP/TCP identification, configurable filtering, packet counters, and MAC address modification.

Simulation & implementation passed · hardware testing pending

VHDLAXI-StreamIPv4 / IPv6

Green digital character rain from the FPGA simulation

HOBBY PROJECT

GENERATIVE VIDEO & ANIMATION

Digital Rain Generator

Falling columns of characters with bright heads and fading green trails, generated entirely in VHDL and displayed over 720p HDMI.

Automatic falling-character demo available

Simulation & implementation passed · hardware testing pending

VHDLCharacter ROM720p HDMI

Zybo board illustration for the FPGA Fireworks Simulator

HOBBY PROJECT

ZYBO · PARTICLE ANIMATION

FPGA Fireworks Simulator

Rockets burst into colorful sparks with fixed-point motion, gravity, and fading. Explore the animated preview.

VHDL720p HDMIParticle Physics

View project →

FROM THE BLOG

Latest Articles

Explore practical FPGA design ideas, engineering decisions, and lessons from my projects.

Explore the Blog

FROM THE BLOG

Build Your FPGA Knowledge

Read in order: start with the foundations, explore practical designs, then tackle advanced integration. Board images are concept illustrations.

View All Articles →

Handwritten-style block diagram of Zynq PS and PL, their AXI connection, and external DDR memory

Step 1 · Foundations

ZYNQ & HARDWARE/SOFTWARE DESIGN

Zynq PS vs PL: Understanding Hardware/Software Partitioning

A simple guide to choosing what runs in software, what becomes hardware, and how the two work together.

8 min read · Read article →

Concept illustration of VHDL design review and verification

Step 2 · Foundations

VHDL DESIGN & VERIFICATION

10 Common RTL Design Mistakes and How to Avoid Them

Practical lessons for FPGA designers, illustrated in VHDL.

10 min read · Read article →

Step 3 · Foundations

VHDL & VERIFICATION

Building a Useful VHDL Testbench

Self-checking tests, corner cases, and clear failure messages, explained through a complete counter example.

9 min read · Read article →

Concept illustration of setup and hold timing

Step 4 · Foundations

FPGA DESIGN & TIMING

Understanding Setup and Hold Timing

A practical guide to timing reports, negative slack, pipelining, and choosing the right fix.

7 min read · Read article →

Step 5 · Foundations

FPGA PERFORMANCE & PIPELINING

Throughput vs Latency: A Common FPGA Design Misunderstanding

How a pipeline can take 20 cycles to produce a result while still accepting a new sample every clock.

5 min read · Read article →

Step 6 · Foundations

FPGA ARCHITECTURE & RESET

Why Reset Architecture Matters More Than It Looks

Choosing reset behavior, initialization, and recovery rules for reliable FPGA systems with several clock domains.

5 min read · Read article →

Step 7 · Practical designs

GAME LOGIC & VIDEO

Building a Pong Game in VHDL

How frame-based game updates, debounced controls, and a pixel renderer fit into a small FPGA game.

2 min read

Step 8 · Practical designs

VIDEO & IMAGE PROCESSING

Designing an HDMI Image-Processing Pipeline

A look at streaming filters, matched timing, and memory tradeoffs in a VHDL video pipeline.

2 min read

Step 9 · Practical designs

AUDIO & DIGITAL SIGNAL PROCESSING

Visualizing Audio with a 256-Point FFT

How an audio sample tap, fixed-point FFT, and clock-domain handshakes drive a 32-band HDMI display.

2 min read

Concept illustration of simulation and hardware validation

Step 10 · Advanced integration

FPGA VERIFICATION & HARDWARE

Simulation Passes—What Comes Next?

What a passing simulation demonstrates, what it leaves open, and how I approach implementation checks and hardware testing.

7 min read · Read article →

Step 11 · Advanced integration

FPGA VERIFICATION & VALIDATION

Why Passing Simulation Is Only the Beginning of FPGA Verification

A practical verification roadmap from checked RTL behavior to timing, board debug, and system-level evidence.

5 min read · Read article →

Concept illustration of reset handling across clock domains

Step 12 · Advanced integration

FPGA DESIGN & RESET

Reset Design Across Clock Domains

Asynchronous assertion, synchronous release, and a practical VHDL example showing why each clock domain needs its own reset handling.

8 min read · Read article →

Concept illustration of clock-domain crossing and coherent transfers

Step 13 · Advanced integration

FPGA DESIGN & VERIFICATION

Clock Domain Crossing: Why Two Synchronizers May Not Be Enough

Understanding independent signal arrival, reconvergence, and coherent transfers with handshakes, valid protocols, and asynchronous FIFOs.

8 min read

Step 14 · Advanced integration

FPGA ARCHITECTURE & TIMING

Timing Closure Is an Architecture Problem, Not Just a Tool Problem

How critical paths, pipeline boundaries, FPGA resources, and physical connections shape timing from the start.

5 min read · Read article →

Step 15 · Advanced integration

IMAGE PROCESSING · VHDL & HLS

VHDL or HLS: Case Study

What my Sobel filter reveals about streaming image processing, explicit RTL control, and where HLS can make algorithm development easier.

8 min read · Read article →

Multiply-add pipeline with matching operand and valid delays

Step 16 · Advanced integration

FPGA ARCHITECTURE & DESIGN

FPGA Architecture: The Decisions Before the RTL

Pipeline boundaries, shared hardware, clock crossings, and the interface decisions that shape an FPGA design before coding starts.

7 min read · Read article →

Streaming image-processing blocks illustrating the architecture choices behind my hobby projects

Step 17 · Reflection

PERSONAL PROJECTS & ENGINEERING LESSONS

What I Learned Building My FPGA Hobby Projects

How my personal projects reflect the way I approach design, testing, problem-solving, and teamwork.

5 min read · Read article →

My FPGA Hobby Projects

Experience across industry applications.

HDMI Video Interface and Image Processing ↗

Audio Spectrum Visualizer ↗

Pong Game ↗

USB Webcam to HDMI ↗

FPGA Logic Analyzer ↗

IPScope — Hardware IP Profiling ↗

High-Speed Ethernet Packet Processing Engine ↗

Digital Rain Generator ↗

FPGA Fireworks Simulator

Latest Articles

Build Your FPGA Knowledge

Zynq PS vs PL: Understanding Hardware/Software Partitioning

10 Common RTL Design Mistakes and How to Avoid Them

Building a Useful VHDL Testbench

Understanding Setup and Hold Timing

Throughput vs Latency: A Common FPGA Design Misunderstanding

Why Reset Architecture Matters More Than It Looks

Building a Pong Game in VHDL

Designing an HDMI Image-Processing Pipeline

Visualizing Audio with a 256-Point FFT

Simulation Passes—What Comes Next?

Why Passing Simulation Is Only the Beginning of FPGA Verification

Reset Design Across Clock Domains

Clock Domain Crossing: Why Two Synchronizers May Not Be Enough

Timing Closure Is an Architecture Problem, Not Just a Tool Problem

VHDL or HLS: Case Study

FPGA Architecture: The Decisions Before the RTL

What I Learned Building My FPGA Hobby Projects

HDMI Video Interface and Image Processing

Audio Spectrum Visualizer

Pong Game

USB Webcam to HDMI

FPGA Logic Analyzer

IPScope — Hardware IP Profiling

High-Speed Ethernet Packet Processing Engine

Digital Rain Generator