10+ YEARS OF PROFESSIONAL ENGINEERING
FPGA Architecture | VHDL | Low-Latency Systems
Video & Image Processing | Embedded Systems
Hardware/Software Co-Design | AI-Assisted Engineering
FROM INPUT TO IMPACT HIGH-LEVEL CONCEPT
FEATURED PROJECTS
Personal projects exploring video, audio, game logic, and embedded systems.
Personal FPGA projects, documented from the repository. Each case study distinguishes implemented features, recorded validation, and work still in progress. Board images are concept illustrations.
HOBBY PROJECTVIDEO & IMAGE PROCESSING
An HDMI video pipeline with selectable edge detection, motion detection, cartoon styling, and color corrections.
Automatic demo available
Implemented · hardware validation not documented
HOBBY PROJECTAUDIO & DIGITAL SIGNAL PROCESSING
Stereo audio loopback with a 256-point FFT and a 32-band spectrum display over HDMI.
Automatic demo available
Simulation & build passed · hardware testing pending
HOBBY PROJECTGAME LOGIC & VIDEO
Two-player Pong in programmable logic, with onboard button controls, collision detection, and a 720p renderer.
Automatic demo available
Simulation & build passed · hardware testing pending
IN DEVELOPMENTEMBEDDED VIDEO · WORK IN PROGRESS
A development project exploring USB webcam capture, frame processing, and HDMI output on PYNQ-Z2.
Automatic demo available
In development
HOBBY PROJECTFPGA DEBUGGING & UART
A self-contained four-channel analyzer with internal UART capture, byte decoding, timing cursors, and a 720p HDMI display.
Automatic demo available
Simulation & implementation passed · hardware testing pending
HOBBY PROJECTHARDWARE IP PROFILING & VERIFICATION
A standalone FIFO characterization instrument measuring throughput, stalls, occupancy, latency, and data integrity on a 720p HDMI dashboard.
Automatic demo available
Simulation preview available · hardware validation pending
HOBBY PROJECTETHERNET & STREAM PROCESSING
A reusable VHDL packet engine with IPv4/IPv6 parsing, UDP/TCP identification, configurable filtering, packet counters, and MAC address modification.
Simulation & implementation passed · hardware testing pending
HOBBY PROJECTGENERATIVE VIDEO & ANIMATION
Falling columns of characters with bright heads and fading green trails, generated entirely in VHDL and displayed over 720p HDMI.
Automatic falling-character demo available
Simulation & implementation passed · hardware testing pending
HOBBY PROJECTZYBO · PARTICLE ANIMATION
Rockets burst into colorful sparks with fixed-point motion, gravity, and fading. Explore the animated preview.
View project →FROM THE BLOG
Read in order: start with the foundations, explore practical designs, then tackle advanced integration. Board images are concept illustrations.
Step 1 · Foundations
ZYNQ & HARDWARE/SOFTWARE DESIGN
A simple guide to choosing what runs in software, what becomes hardware, and how the two work together.
8 min read · Read article →
Step 2 · Foundations
VHDL DESIGN & VERIFICATION
Practical lessons for FPGA designers, illustrated in VHDL.
10 min read · Read article →Step 3 · Foundations
VHDL & VERIFICATION
Self-checking tests, corner cases, and clear failure messages, explained through a complete counter example.
9 min read · Read article →
Step 4 · Foundations
FPGA DESIGN & TIMING
A practical guide to timing reports, negative slack, pipelining, and choosing the right fix.
7 min read · Read article →
Step 5 · Foundations
FPGA PERFORMANCE & PIPELINING
How a pipeline can take 20 cycles to produce a result while still accepting a new sample every clock.
5 min read · Read article →
Step 6 · Foundations
FPGA ARCHITECTURE & RESET
Choosing reset behavior, initialization, and recovery rules for reliable FPGA systems with several clock domains.
5 min read · Read article →Step 7 · Practical designs
GAME LOGIC & VIDEO
How frame-based game updates, debounced controls, and a pixel renderer fit into a small FPGA game.
2 min readStep 8 · Practical designs
VIDEO & IMAGE PROCESSING
A look at streaming filters, matched timing, and memory tradeoffs in a VHDL video pipeline.
2 min readStep 9 · Practical designs
AUDIO & DIGITAL SIGNAL PROCESSING
How an audio sample tap, fixed-point FFT, and clock-domain handshakes drive a 32-band HDMI display.
2 min read
Step 10 · Advanced integration
FPGA VERIFICATION & HARDWARE
What a passing simulation demonstrates, what it leaves open, and how I approach implementation checks and hardware testing.
7 min read · Read article →
Step 11 · Advanced integration
FPGA VERIFICATION & VALIDATION
A practical verification roadmap from checked RTL behavior to timing, board debug, and system-level evidence.
5 min read · Read article →
Step 12 · Advanced integration
FPGA DESIGN & RESET
Asynchronous assertion, synchronous release, and a practical VHDL example showing why each clock domain needs its own reset handling.
8 min read · Read article →
Step 13 · Advanced integration
FPGA DESIGN & VERIFICATION
Understanding independent signal arrival, reconvergence, and coherent transfers with handshakes, valid protocols, and asynchronous FIFOs.
8 min read
Step 14 · Advanced integration
FPGA ARCHITECTURE & TIMING
How critical paths, pipeline boundaries, FPGA resources, and physical connections shape timing from the start.
5 min read · Read article →Step 15 · Advanced integration
IMAGE PROCESSING · VHDL & HLS
What my Sobel filter reveals about streaming image processing, explicit RTL control, and where HLS can make algorithm development easier.
8 min read · Read article →
Step 16 · Advanced integration
FPGA ARCHITECTURE & DESIGN
Pipeline boundaries, shared hardware, clock crossings, and the interface decisions that shape an FPGA design before coding starts.
7 min read · Read article →
Step 17 · Reflection
PERSONAL PROJECTS & ENGINEERING LESSONS
How my personal projects reflect the way I approach design, testing, problem-solving, and teamwork.
5 min read · Read article →ENGINEERING PERSPECTIVES
Thoughts on the decisions that make hardware and software work well together.
HARDWARE / SOFTWARE CO-DESIGN
Why predictable interfaces, clear hardware behavior, and thoughtful FPGA architecture make software integration easier.
By Adeel Akhtar · 6 min read
Read insight →ABOUT ME
I’m Adeel Akhtar, a Senior FPGA & Embedded Systems Engineer with more than 10 years of professional engineering experience.
My technical focus spans FPGA architecture, VHDL, low-latency systems, video and image processing, embedded systems, hardware/software co-design, and AI-assisted engineering.
More about me →Education →PROFESSIONAL EXPERIENCE
Project case studies will highlight the requirements, challenges, and outcomes behind the work.
Explore experience →HOW I APPROACH ENGINEERING
From video filters to hardware debugging, my personal projects help me explore ideas and make design choices clear. They reflect how I approach a problem: understand the limits, build a manageable system, test its behavior, and explain the results.
I share the lessons behind these projects—and the approach I would bring to an engineering team.
Read my story
LET’S BUILD WHAT COMES NEXT
I welcome conversations about FPGA design, embedded systems, and opportunities for cooperation.